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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a quad 8-bit voltage out cmos dac complete with internal 10 v reference dac8426 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the dac8426 is a complete quad voltage output d/a converter with internal reference. this product fits directly into any exist- ing 7226 socket where the user currently has a 10 v external reference. the external reference is no longer necessary. the internal reference of the dac8426 is laser-trimmed to 0.4% features no adjustments required, total error 6 1 lsb max over temperature four voltage-output dacs on a single chip internal 10 v bandgap reference operates from single 1 15 v supply fast 50 ns data load time, all temperatures pin-for-pin replacement for pm-7226 and ad7226, eliminates external reference applications process controls multichannel microprocessor controlled: system calibration op amp offset and gain adjust level and threshold setting offering a 25 ppm/ c temperature coefficient and 5 ma of exter- nal load driving capability. the dac8426 contains four 8-bit voltage-output cmos d/a converters on a single chip. a 10 v output bandgap reference sets the output full-scale voltage. the circuit also includes four input latches and interface control logic. one of the four latches, selected by the address inputs, is loaded from the 8-bit data bus input when the write strobe is active low. all digital inputs are ttl/cmos (5 v) compatible. the on-board amplifiers can drive up to 10 ma from either a single or dual supply. the on-board reference that is always connected to the internal dacs has 5 ma available to drive external devices. its compact size, low power, and economical cost-per-channel, make the dac8426 attractive for applications requiring mul- tiple d/a converters without sacrificing circuit-board space. sys- tem reliability is also increased due to reduced parts count. pmis advanced oxide-based, silicon-gate, cmos process al- lows the dac8426s analog and digital circuitry to be manufac- tured on the same chip. this, coupled with pmis highly stable thin-film r-2r resistor ladder, aids in matching and tempera- ture tracking between dacs. functional block diagram
parameter symbol conditions min typ max units static performance resolution n 8 bits total unadjusted error 1 tue includes reference a, e 1 lsb b, f 2 lsb relative accuracy inl a, e 1/2 lsb b, f 1 lsb differential nonlinearity 2 dnl 1 lsb full-scale temperature coefficient tcg fs includes reference 25 ppm/ c zero scale error v zse 20 mv zero scale error temperature coefficient tcv zs dual supply v ss = C5 v 10 m v/ c reference output output voltage v ref out no load a, e 9.96 10.04 v b, f 9.92 10.08 v temperature coefficient tcv ref out 20 ppm/ c load regulation ld reg d i l = 5 ma 0.02 0.1 %/ma line regulation ln reg d v dd 10% 0.008 0.04 %/v output noise 3 e n rms f = 0.1 hz to 10 hz 3 10 m v p-p output current i ref out d v ref out < 40 mv 5 7 ma digital inputs logic input 0 v inl 0.8 v logic input 1 v inh 2.4 v input current i in v in = 0 v or v dd 0.1 10 m a input capacitance 3 c in 48pf power supplies positive supply current 4 i dd 614ma negative supply current 4 i ss dual supply v ss = C5 v 4 10 ma power dissipation 5 p diss 90 210 mw power supply sensitivity p ss d v dd = 5% 0.0002 0.01 %/% rev. c C2C dac8426Cspecifications (v dd = +15 v 6 10%, agnd = dgnd = 0 v, v ss = 0 v, t a = C55 8 c to +125 8 c applies for dac8426ar/br, t a = C40 8 c to +85 8 c applies for dac8426er/ep/fr/fp/fs, unless otherwise noted.) parameter symbol conditions min typ 6 max units dac output output current (source) 3 i out source digital in = all ones 10 ma output current (sink) 3 i out sink digital in = all zeroes v ss = C5 v 350 450 m a minimum load resistance r l(min) digital in = all ones 2 k w dynamic performance 3 v out slew rate sr 4 v/ m s v out settling time t s to 1/2 lsb, r l = 2 k w 3 m s (positive or negative) digital crosstalk q 10 nvs switching characteristics 3 address to write setup time t as 0ns address to write hold time t ah 0ns data valid to write setup time t ds 70 ns data valid to write hold time t dh 10 ns write pulse width t wr 50 ns notes 1 includes full-scale error, relative accuracy, and zero code error. note 1 lsb = 0.39% error. 2 all devices guaranteed monotonic over the full operating temperature range. 3 guaranteed and not subject to production test. 4 digital inputs v in = v inl or v inh ; v out and v ref out unloaded. 5 p diss calculated by i dd v dd . 6 typicals represent measured characteristics at t a = +25 c. specifications subject to change without notice. electrical characteristics v dd = +15 v 6 10%, agnd = dgnd = 0 v, v ss = 0 v, t a = C55 8 c to +125 8 c applies for dac8426ar/br, t a = C40 8 c to +85 8 c applies for dac8426er/ep/fr/fp/fs, unless otherwise noted.
dac8426 C3C rev. c caution 1. do not apply voltages higher than v dd or less than v ss po- tential on any terminal. 2. the digital control inputs are zener-protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. keep units in conductive foam at all times until ready to use. 3. do not insert this device into powered sockets. remove power before insertion or removal. 4. stresses above those listed under absolute maximum rat- ings may cause permanent damage to device. burn-in circuit absolute maximum ratings v dd to agnd or dgnd . . . . . . . . . . . . . . . . . C0.3 v, +17 v v ss to agnd or dgnd . . . . . . . . . . . . . . . . . . . . . C7 v, v dd v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +24 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +5 v digital input voltage to dgnd . . . . . . . . . . . . . C0.3 v, v dd v ref out to agnd 1 . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd v out to agnd 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd operating temperature military ar/br . . . . . . . . . . . . . . . . . . . . C55 c to +125 c extended industrial er/ep/fr/fp/fs . . . . C40 c to +85 c maximum junction temperature . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . +300 c thermal resistance package type u ja 2 u jc units 20-pin cerdip (r) 70 7 c/w 20-pin plastic dip (p) 61 24 c/w 20-pin sol(s) 80 22 c/w notes 1 outputs may be shorted to any terminal provided the package power dissipation is not exceeded. typical output short-circuit current to agnd is 50 ma. 2 q ja is specified for worst case mounting conditions, i.e., q ja is specified for de- vice in socket for cerdip and p-dip packages; q ja is specified for device sol- dered to printed circuit board for sol package. 20-pin cerdip (r suffix) 20-pin epoxy dip (p suffix) 20-pin sol (s suffix) pin connections ordering guide 1 model total unadjusted error temperature range package description dac8426ar 2 1 lsb C55 c to +125 c 20-pin cerdip (q-20) dac8426er 1 lsb C40 c to +85 c 20-pin cerdip (q-20) dac8426ep 1 lsb C40 c to +85 c 20-pin plastic dip (n-20) dac8426br 2 2 lsb C55 c to +125 c 20-pin cerdip (q-20) dac8426fr 2 lsb C40 c to +85 c 20-pin cerdip (q-20) dac8426fp 2 lsb C40 c to +85 c 20-pin plastic dip (n-20) dac8426fs 3 2 lsb C40 c to +85 c 20-lead sol (r-20) notes 1 burn-in is available on commercial and industrial temperature range parts in cerdip, plastic dip, and to-can packages. 2 for devices processed in total compliance to mil-std-883, add /883 after part number. consult factory for 883 data sheet. 3 for availability and burn-in information on so and plcc packages, contact your local sales office.
dac8426 C4C rev. c dice characteristics die size 0.129 0.152 inch, 19,608 sq. mils (3.28 3.86 mm, 12.65 sq. mm) 1. v out b 11. db 3 2. v out a 12. db 2 3. v ss 13. db 1 4. v ref out 14. db 0 (lsb) 5. agnd 15. wr 6. dgnd 16. a 1 7. db 7 (msb) 17. a 0 8. db 6 18. v dd 9. db 5 19. v out d 10. db 4 20. v out c warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the dac8426 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. dac8426gbc parameter symbol conditions limits units total unadjusted error tue 2 lsb max relative accuracy inl 1 lsb max differential nonlinearity dnl 1 lsb max full-scale error g fse 1 lsb max zero code error v zse 20 mv max dac output current i out source digital in = all ones 10 ma min reference output voltage v ref out no load 10.04 v max load regulation ld reg d i l = 5 ma 0.1 %/ma max line regulation ln reg d v dd = 10 v 0.04 %/v max reference output current i ref out d v ref out < 40 mv 5 ma min logic inputs high v inh 2.4 v min logic inputs low v inl 0.8 v max logic input current i in v in = 0 v or v dd 1 m a max positive supply current i dd v in = v inl or v inh 14 ma max negative supply current i ss v in = v inl or v inh v ss = C5 v 10 ma max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. wafer test limits at v dd = +15 v 6 5%; v ss = agnd = dgnd = 0 v; unless otherwise specified. t a = +25 8 c. all specifications apply for dacs a, b, c, and d.
typical performance characteristicsC dac8426 C5C rev. c channel-to-channel matching (dacs a, b, c, d, superimposed) long term drift accelerated by burn-in power supply current vs. temperature zero code error vs. temperature broadband noise (dc to 200 khz) psrr (+) = C20 log v out (0) d v dd ? ? ? ? , v dd = +15 v 6 1 v p , v ss = 0 v psrr (C) = C20 log v out (0) d v ss ? ? ? ? , v dd = +15 v, v ss = C4 v 6 1 v p relative accuracy vs. code at t a = C55 c, +25 c, +125 c (all superimposed) v out noise density vs. frequency psrr vs. frequency
dac8426C typical performance characteristics C6C rev. c v ref out error from 10.000 v vs. temperature output impedance (v ref out) vs. frequency v ref out load regulation vs. temperature v ref out start up v ref out line regulation vs. temperature
dac8426 C7C rev. c parameter definitions total unadjusted error (tue) this specification includes the full-scale-error, relative accu- racy zero-code-error and the internal reference voltage. the ideal full-scale output voltage is 10 v minus 1 lsb which equals 9.961 volts. each lsb equals 10 v (1/256) = 0.039 volts. digital crosstalk digital crosstalk is the signal coupled to the output of a dac due to a changing digital input from adjacent dacs being up- dated. it is specified in nano-volt-seconds (nvs). circuit description the dac8426 is a complete quad 8-bit d/a converter. it con- tains an internal bandgap reference, four voltage switched r-2r ladder dacs, four dac latches, four output buffer amplifiers, and an address decoder. all four dacs share the internal ten volt reference and analog ground(agnd). figure 1 provides an equivalent dac plus buffer schematic. figure 1. simplified circuit configuration for one dac. (switches are shown for all 1s on the digital inputs.) the eleven digital inputs are compatible with both ttl and 5 v (or higher) cmos logic. table i shows the dac control logic truth table for wr , a 1 , and a 0 operation. when wr is active low the input latch of the selected dac is transparent, and the dacs output responds to the data present on the eight digital data inputs (dbx). the data (dbx) is latched into the ad- dressed dacs latch on the positive edge of the wr control sig- nal. the important timing requirements are shown in the write cycle timing diagram, figure 2. internal 10 volt reference the internal 10 v bandgap reference of the dac8426 is trimm- ed to the output voltage and temperature drift specifications. this internal reference is connected to the reference inputs of the four internal 8-bit d/a converters. the output terminal of the internal 10 v reference is available on pin 4. the 10 v out- put of the reference is produced with respect to the agnd pin. this reference output can be used to supply as much as 5 ma of additional current to external devices. care has been taken in table i. dac control logic truth table logic control dac8426 wr a 1 a 0 operation h x x no operation device not selected l l l dac a transparent g l l dac a latched l l h dac b transparent g l h dac b latched l h l dac c transparent g h l dac c latched l h h dac d transparent g h h dac d latched l = low state, h = high state, x = dont care figure 2. write cycle timing diagram the design of the internal dac switching to minimize transients on the reference voltage terminal (v ref out). other devices connected to this reference terminal should have well behaved input loading characteristics. d/a converters such as the pmi pm7226a have been designed to minimize reference input tran- sient currents and can be directly connected to the dac8426 10 v reference. devices exhibiting large current transients due to internal switching should be buffered with an op amp to maintain good overall system noise performance. a 10 m f refer- ence output bypass capacitor is required. buffer amplifier section the four internal unity-gain voltage buffers provide low output impedance capable of sourcing 5 ma or sinking 350 m a. typical output slew rates of 4 v/ m s are achieved with 10 v full-scale out- put changes and r l = 2 k w . figure 3 photographs show large sig- nal and settling time response. capacitive loads to 3300 pf maximum, and resistive loads to 2 k w minimum can be applied.
dac8426 C8C rev. c a) large signal b) settling time response (negative transition) c) settling time response (positive transition) figure 3. dynamic response the outputs can withstand an indefinite short-circuit to agnd to typically 50 ma. the output may also be shorted to any volt- age between v dd and v ss ; however, care must be taken to not exceed the device maximum power dissipation. the amplifiers emitter follower output stage consists of an in- trinsic npn bipolar transistor with a 400 m a nmos pull-down current-source load connected to v ss . this circuit configuration shown in figure 4 enables the output amplifier to develop out- put voltages very close to agnd. only the negative supply of the four output buffer amplifiers are connected to v ss . operating the dac8426 from dual supplies (v dd = +15 v and v ss = C5 v) improves negative going output settling time near zero volts. when operating single supply (v dd = +15 v and v ss = 0 v) the output sink current decreases as the output approaches zero voltage. within 200 mv of agnd (single-supply operation) the internal sinking capability appears resistive at a value of approxi- mately 1200 w . the buffer amplifier output current and voltage characteristics are plotted in figure 5. test conditions, all photos: v dd = +15 v c ref out = 10 m f r l = 2 k v digital input sequence 0, 255, 0
dac8426 C9C rev. c applications setup unipolar output operation the output voltage appearing at any output v out is equal to the internal 10 v reference multiplied by the decimal value of the latched digital input divided by 2 8 (= 256). in equation form: v out ( d ) = d /256 10 v where d = 0 10 to 255 10 figure 4. amplifier output stage note that the maximum possible output is 1 lsb less than the internal 10 v reference, that is, 255/256 10 v = 9.961 v. table ii lists output voltages for a given digital input. the total unadjusted error (tue) specification of the product grade used determines the output tolerances of the values listed in table ii. for example, a 2 lsb grade dac8426fp loaded with decimal 128 10 (half-scale) would have a guaranteed output voltage oc- curring in the range of 5 v 2 lsb, which is 5 v (2 10 v/256) = 5 v 0.078 v. therefore v out is guaranteed to occur in the following range: 4.922 v v out ( 128 ) 5.078 v figure 5. dac output current sink for the top grade dac8426ep 1 lsb total unadjusted error (tue), the guaranteed range is 4.961 v v out (128 10 ) 5.039 v. these tolerances provide the worst case analysis including tem- perature changes. one additional characteristic guaranteed is a dnl of 1 lsb on all grades. the dac8426 is therefore guaranteed to be mon- otonic. in the situation where a continuously positive 1 lsb digital increment is applied, the output voltage will always in- crease in value, never decrease. this is very important is servo applications and other closed-loop feedback systems. finally, in the typical characteristic curves, long term output voltage drift (stability) is provided. bipolar output operation an external op amp plus two resistors can easily convert any dac output to bipolar output voltage swings. figure 6 shows all four dacs output operating in bipolar mode. this is the general expression describing the bipolar output transfer equation: v out ( d ) = [(1 + r 2 / r 1 ) d /256 10 v ] C r 2 /r 1 10 v , where d = 0 10 to 255 10 if r 1 = r 2 , then v out becomes: v out ( d ) = ( d /128C1) 10 v table iii lists various output voltages with r 1 = r 2 versus digital input code. this coding is considered offset binary. note that the lsb step size is now 20 v/256 = 0.078 v, twice as large as the unipolar output case previously discussed. in order to minimize gain and offset errors, choose r 1 and r 2 to match and track within 0.1% over the selected operating temperature range of interest. table ii. unipolar output voltage as a function of digital input code digital input analog output code voltage (= d/256 10 v) 255 9.961 v full-scale (fs) 254 9.922 v fs-1 lsb 129 5.039 v 128 5.000 v half-scale 127 4.961 v 1 0.039 v 1 lsb 0 0.000 v zero-scale offsetting agnd since the dac ladder and bandgap reference are terminated at agnd, it is possible to offset agnd positive with respect to dgnd. the 10 v output span remains if a positive offset is ap- plied to agnd. the offset voltage source connected to agnd must be capable of sinking 14 ma. agnd cannot be taken negative with respect to dgnd; this would forward bias an in- ternal diode. allowance must be made at v dd to maintain 3.5 v of headroom above v ref out. this connection setup is useful in single supply applications where virtual ground needs to be slightly positive with respect to ground. in this application con- nect v ss to dgnd to take advantage of the extra buffer output current sinking capability when the dac output is programmed to all zeros code, see figure 7.
dac8426 C10C rev. c figure 6. bipolar operation connection and layout guidelines layout and design techniques used in the interface between dig- ital and analog circuitry require special attention to detail. the following considerations should be evaluated prior to pcb layout. 1. return signal paths through the ground system should be carefully considered. high-speed digital logic current pulses traveling on return ground traces generate glitches that can be radiated to the analog circuits if the ground path layout pro- duces loop antennas. ground planes can minimize this situa- tion. separate digital and analog grounding areas to minimize crosstalk. ideally a single common-point ground should be on the same pcb board as the dac8426. the analog ground re- turns should take advantage of the appropriate placement of power supply bypass capacitors. 2. for optimum performance, bypass v dd and v ss (if using negative supply voltage) with 0.1 m f ceramic disk capacitors to shunt high-frequency spikes. also use in parallel 6.8 m f to 10 m f capacitors to provide a charge reservoir for lower fre- quency load change requirements. the reference output (v ref out) should be bypassed with a 10 m f tantalum ca- pacitor to optimize reference output stability during data in- put changes. this helps to minimize digital crosstalk. table iii. bipolar output voltage as a function of digital input code digital input analog output code voltage (= d/256 10 v) 255 9.922 v full-scale (fs) 254 9.844 v fs-1 lsb 129 0.078 v 128 0.000 v zero-scale 127 C0.078 v 1 C9.922 v 0 C10.000 v neg full-scale figure 7. agnd biasing scheme providing offset output range 3. power supply sequencingno special requirements exist with the dac8426. however, users should be aware that of- ten the 5 v logic supply may be powered up momentarily prior to the +15 v analog supply. in this situation, the dac8426 esd input protection diodes will forward bias if the applied input logic is at logic 1. no damage will result to the input since the dac8426 is designed to withstand mo- mentary currents of up to 130 ma. this situation will likely exist for any dac or adc operating from a separate analog supply. 4. esd input protectionattention has been given in the de- sign of the dac8426 to esd sensitivity. using the human body model test technique (mil-std 3015.4) the dac8426 generally will withstand 1500 v esd transients on all pins. handling and testing prior to pcb insertion generally exposes ics to the toughest environment they will experience. once the ic is soldered in the pcb, it is still important to consider any traces that connect to pcb edge connectors. these traces should be protected with appropriate devices especially if the boards will experience field replacement or adjustment. han- dling the exposed edge connectors by field maintenance people in a low humidity environment can produce 20 kv esd transients which will be detrimental to almost any inte- grated ic connected to the edge connector.
dac8426 C11C rev. c microprocessor interfacing the dac8426 easily interfaces to most 8- and 16-bit wide data- bus systems. serial and 4-bit busses can also be accommodated with additional latches and control circuitry. interfacing can be accomplished with databus transfers running with 50 ns write pulse widths. examples of various microprocessor interface circuits are pro- vided in figures 8 through 12. these figures have omitted cir- cuitry not essential to the bus interface. the design process should include review of the dac8426 timing diagram with the m p system timing diagram. figure 8. dac8426 to 8085a interface (simplified circuit, only lines of interest are shown.) figure 9. dac8426 to z-80 interface (simplified circuit, only lines of interest are shown.) figure 10. dac8426 to 6809 interface (simplified circuit, only lines of interest are shown.) figure 11. dac8426 to 6502 interface (simplified circuit, only lines of interest are shown.) figure 12. dac8426 to 68000 interface (simplified circuit, only lines of interest are shown.)
dac8426 C12C rev. c 000000000 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 20-pin cerdip (q-20) 20 1 10 11 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 1.060 (26.92) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 20-pin plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead sol (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20 11 10 1 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1

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